## Supplementary Codes for Scalable and Robust Multi-Bit Spintronic Synapses for Analog In-Memory Computing

**Kshemal K. Gupte Sohan Salahuddin Mugdho Cheng Wang**

Iowa State University

# Multi-state MRAM Sensing Section
# Using Cadence Virtuoso

This section contains simplified guide for using the VerilogA file.

## To design schematic 
1. Create a new Library in Cadence Virtuoso and attach available technology PDK such as TSMC 0.18um.
2. Copy the `multigrain_mtj` folder in your Cadence Virtuoso Library.  
3. Create a new schematic cell view in the same library. Click on `i` to add instance, browse and select the corresponding library and cell that contains the Veriloga code. Click anywhere on the schematic window to place the instance.
4. Replace appropriate tox, anneal_ra_p, anneal_ra_ap values for multi-state MRAM.
5. Create the sense amplifier circuit from the main paper to simulate the MTJ.

## To simulate
6. Go to Launch->ADE Explorer->Create New View->(If the cell section says `maestro`) Click OK.
7. In the Analysis tab, click on `Click to add analysis` and select transient analysis.
8. Go to Outputs->To be plotted->Select from design. Select outputs to be plotted and Run Simulation to generate results.